In order to correctly read a data item from a memory cell of a memory matrix, a current read from a memory matrix cell may be compared to a current read from a reference matrix cell, which may be different matrices. In this manner, the difference between a programmed cell and an erased cell may be detected. In addition, rather than using a reference cell current, several kinds of current generators could be also used in place of them.
For this reason, memory matrices may be configured so that a reading of the data item from a memory cell is obtained by comparing a current that flows across a reference matrix cell with a current of a selected cell. In the current state of the art, this may be accomplished by the use of “mirror sensing” where Pchannel transistors operate in a mirror and diode configuration. Pchannel transistors must be able to furnish a very high current to quickly precharge a large capacitance and need to have a large length in order to minimize possible mirror error. Accordingly, Pchannel transistors have a large width and length, which causes them to take up a large surface area on a circuit.
Due to the large lengths (L) and widths (W), Pchannel transistors have a high capacitance load. Therefore, after the precharge phase, when they are required to sink a very low current, (e.g., the flash cell current that is in the range of uA), they are already near their turning off point, and their large capacitance load in this state must be moved by a low current. The large size of the Pchannel transistors is required to sink a high current to quickly precharge the bitline capacitance. Additionally, they are not effective for low current. Using a Pchannel transistor, or diode configuration, to precharge a node has an additional drawback in that the last precharge phase is very slow because as the voltage of the node increases, which is also the voltage in the gate to the Pchannel transistor, the transistor current is decreasing.